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WEDNESDAY, Sept 1

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14:00 - 14:30        Introduction (P. Marwedel)

14:30 - 16:00        SESSION 1: Retargetable compilation and run-time analysis

              "An automatic system for application-specific instruction
               format design and code generation for VLIW and EPIC processors"

               S. Aditya, S. Mahlke, B. Rau, R. Johnson
               HP Labs, USA

               "A retargetable approach to calculate run-time guarantees for real-time systems"

               C. Ferdinand, D. Kaestner, M. Langenbach,
               F. Martin, M. Schmidt, J. Schneider,
               H. Theiling, S. Thesing, R. Wilhelm
             University of Saarbruecken, Germany

              "Constraint analysis for code generation: basic techniques and
               their applications in FACTS"

              B. Mesman, C.A. Pinto, K. van Eijk, J. van Meerbergen, J. Jess
              Philips Research Labs, The Netherlands

             "Graph based code selection techniques for embedded processors"
               (Part I, Part II)

              R. Leupers, S. Bashford, P. Marwedel

              University of Dortmund, Germany

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THURSDAY, Sept 2

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09:15 - 10:30        SESSION 3: Invited Talk

              "Cost-efficient system design for embedded multimedia applications"

               Lode Nachtergaele, Francky Cathoor
               IMEC, Belgium
 

11:00 - 12:30       SESSION 4: DSP tool design with the CoSy system

             "DSP-C application simulation using CoSy"

              J. van Dongen, M. de Jong, H. van Someren
              ACE, The Netherlands

            "Optimized code generation for the TI TMS320C54x"

              A. Ropers, H. Meyr
              RWTH Aachen, Germany
 

14:00 - 15:30       SESSION 5: DSP code optimization

             "Simulated evolutionary optimization of DSP programs"

              B. Wess, T. Zeitlhofer
              TU Vienna, Austria

            "Optimal and heuristic solutions for minimizing costs of
               local variables access for DSPs"

              E. Eckstein, A. Krall
              TU Vienna, Austria

16:00 - 18:15       SESSION 6: System-level optimization and estimation

            "Systematic expansion of single appearance schedules"

              S. Bhattacharyya, P. K. Murthy
              University of Maryland/Angeles Design Systems, USA

            "Retargetable estimation scheme for DSP architecture selection"

              N.S. Ghazal, A.R. Newton, J.M. Rabaey
              UC Berkeley, USA

             "Retargetable compilation for embedded system design considering variable precisions"

              A. Inoue, H. Tomiyama, H. Yasuura
              Kyushu University, Japan

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FRIDAY, Sept 3

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09:00 - 10:30       SESSION 7: Retargetable simulation

            "Automatic generation of a software toolkit from EXPRESSION"

              P. Grun, N. Savoiu, A. Nicolau, N. Dutt
              UC Irvine, USA

            "A retargetable tool suite for embedded processors based on LISA"

              A. Hoffmann, S. Pees, H. Meyr
              RWTH Aachen, Germany

11:00 - 12:30       SESSION 8: VLIW code generation

 
            "Using iterative compilation for managing software pipeline-unrolling tradeoffs"

              P. van der Mark, E. Rohou, F. Bodin, Z. Chamski, C. Eisenbeis
              Inria, France / Philips Research Labs, The Netherlands

            "Flexible issue slot assignment for VLIW architectures"
              (Paper)

              Z. Chamski, C. Eisenbeis, E. Rohou,
              Inria, France / Philips Research Labs, The Netherlands

14:00 - 15:30        SESSION 9: Novel research directions

 
             "Flow graph based parallel code generation"

               A. Roemer, G. Fettweis
               TU Dresden, Germany
 
 

              "Formal verification of DSP software"

               D. Currie, A. Hu, S. Rajan, M. Fujita
               Univ. of British Columbia, Canada / Fujitsu Labs of America, USA